Talk : Low-Power Circuit Optimization with Multi-Bit Registers

报告时间：2019年1月7号，9:30am-11:00am

报告地点：数计学院4号楼229室

Abstract:

With limited power/thermal budgets for modern system on chips (SoCs), power minimization has become one of the most important objectives in designing SoCs for various wearable or handheld applications. Higher power dissipation will not only increase system costs but also affect lifetime and reliability. As the process technology advances, applying multi-bit registers becomes promising for minimizing dynamic and leakage power, and hence achieving ultra-low-power design. This talk will introduce some applications of applying multi-bit registers, including clock network minimization, flip-flop state retention due to power gating, and timing/reliability enhancement for time-borrowing and local-boosting error-resilient circuits. The review of the related work and the state-of-the-art design methodologies will also be presented.

Bio:

Mark Po-Hung Lin received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University (NCTU), Hsinchu, Taiwan, and the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan. He is currently a professor in the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan. His research interests lie in the field of electronic design automation (EDA), particularly in design automation for analog/mixed-signal/RF integrated circuits and emerging high-performance energy-efficient circuits and systems.

Dr. Lin has 7+ year industrial experience with SpringSoft, Inc. (acquired by Synopsys, Inc.), where he received the 2006 Best SpringSoft R&D Team Award as a technical manager and team leader. He co-initiated the \"Laker Analog Prototyping\" product with 5 patented technologies. He was also a Visiting Research Scholar with the University of Illinois at Urbana-Champaign, Champaign, IL, USA, during 2007–2009, a Humboldt Research Fellow with the Technical University of Munich (TUM), Germany, during 2013–2015, and a JSPS Invitation Fellow with Osaka University, Japan, in 2016. He has been serving in the technical program committees of the premier EDA conferences, including DAC, ICCAD, DATE, ASP-DAC, and ISPD.