Title: Placement for Modern Circuit Designs

Speaker: Chau-Chin Huang黄朝琴博士

National Taiwan University (NTU)台湾大学

Time: 9:30am-11:00am, June 2, 2017

Place: 数计学院4号楼229  第一报名厅

Abstract: Placement is a classical problem in physical design that has been studied for several decades. In recent years, modern design considerations (including performance, routability, and power) have reshaped the placement problem comprehensively. In this talk, we focus on addressing these considerations in respect to resolving the following critical challenges during placement: (1) datapath, (2) technology and fence-region constraints, (3) timing closure, and (4) latch clustering. To improve circuit performance, datapath-aware placement for physical regularity has shown great promise in recent works. However, the lack of widespread industrial adoption indicates this research topic is still unsolved. To improve routability, as technology nodes continuously shrink to 10nm and below, various complex design rules should be satisfied in detailed routing (after placement). Fortunately, some of these rules can be formulated as technology constraints in placement. In addition to technology constraints for routability, fence regions (or move bounds) also impose constraints in placement for better performance. Furthermore, minimizing the interconnection delay during placement is another way to improve circuit performance, mainly because the delay caused by thinner and more resistive wires has become a major bottleneck for timing closure in physical design. Finally, to achieve better power and performance trade-off, latch clustering and placement play important roles in physical design, as the number of latch clusters determines the effectiveness for clock gating (i.e., dynamic power saving) and the placement determines the timing disruption for the clustering process.

Biography: Chau-Chin Huang received the B.S. degree in electrical engineering from National Cheng Kung University (NCKU), Tainan, Taiwan, in 2012. He is currently pursuing the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan. His current research interests focus on placement optimization and datapath extraction. He won the 1st place, 3rd place, and 5th place at the Placement Contests at ICCAD in 2012, 2013, and 2015, respectively, and the 1st place, 2nd place, and 4th place at the Placement Contests at ISPD 2015, 2017, and 2014, respectively. He also published three papers at DAC, one paper at ICCAD, one paper at ASP-DAC, and one paper at TCAD. He was a recipient of an outstanding student scholarship from the EE Department of NCKU in 2009 and a recipient of annual GIEE award in 2012, 2013, 2015, and 2016.